Intel's X25-M revolutionized the SSD market. But then SandForce turned it upside down, coming out of nowhere to establish a dominant position. Today we see the company preview its second-generation controller, unleashed over a native 6 Gb/s interface.
Back in September of last year, we previewed OCZ’s high-speed data link technology in OCZ's HSDL: A New Storage Link For Super-Fast SSDs. This is a PCI Express-based interconnect designed to overcome the limits of conventional SAS and SATA. The argument was that both serial interconnects, which now top out at 6 Gb/s, artificially limit what today's fastest NAND flash devices are capable of.
Granted, most folks are still limited to SATA 3Gb/s. Intel only just added 6 Gb/s support to its problematic Cougar Point chipsets, while AMD's SB850 has offered that capability for a little while longer. But it's not like 3 Gb/s signaling is really holding most of us back anyway. Before the 6 Gb/s interfaces make real sense as differentiators, we need more storage devices capable of saturating the ~300 MB/s a 3 Gb/s link theoretically enables.
Right now, there is a mad rush to bring those next-generation 6 Gb/s devices to market. Crucial's C400 is expected to emerge within the next month and a half. Intel's SSD 510-series drives are just over the horizon as well. But OCZ beat both competitors to getting actual drives into our hands for a performance preview. The Vertex 3 Pro we have is admittedly pre-production and intended for an enterprise audience. But at the end of the day, those are the environments that stand to gain most immediately from a transition to higher-performance storage. And of course, we will be seeing consumer-level drives based on this same technology before long.
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OCZ's Vertex 3 Pro specs, based on SandForce's new and highly-anticipated SF-2582 controller, greatly exceed the only other currently-available 6 Gb/s SSD, Crucial's C300--and not by a slim margin. OCZ is citing sequential reads of up to 550 MB/s and writes as high as 500 MB/s, with 70 000 IOPS in random 4 KB writes.
Flash Memory: SLC & MLC
With the next generation of SSDs on the horizon, it makes sense to cover the basics on how NAND flash works. The typical system memory that we rely on for temporary storage between the drives and our processor (generally DDR3 in today's systems) is volatile in that it requires power for data retention. Once you shut down your computer, all the information in RAM is lost. NAND flash is different. It is non-volatile memory. When you write to a solid-state drive, it holds the data, even after you power down your computer. Unlike platters inside a hard drive, flash memory's ability to hold a charge gives out if it is erased too many times.
There are two main types of NAND memory used in today's SSDs (four if you count eSLC and eMLC but we will save that for another day): Single-Level Cell (SLC) and Multi-Level Cell (MLC). At the manufacturing level, both are nearly identical. The difference is in how data is stored, and that in turn affects performance, reliability, and cost.
A flash cell is made up of a single transistor, with an additional "floating" gate that stores electrons. These electrons are the result of an electrical field generated from the large voltage difference between the drain the and source. This field is what allows the nonconductive silicon substrate to function as a conductive channel. The idea is that, as electrons flow through the channel, the field is used to bump electrons up to the floating gate. However, even as the electron travels down the channel, gaining momentum, the energy gained is insufficient to push the electron onto the gate. Those electrons that already have a high momentum approaching the gate can end up being bumped up into the gate by first hitting a silicon atom within the channel. It is the number of electrons in the floating gate that affects the voltage of the cell, and voltage is used to determine the cell's state.
SLC Levels
|
|---|
Value
| State
|
|---|
0
| Programmed
|
|---|
1
| Erased
|
|---|
How does this relate to data? Single-Level Cell flash stores one bit per cell. It is a single-bit binary system. It is either a "0" or a "1." Since states are dependent on voltage, the electrical charge you induce on the floating gate affects the state.
In the diagram, the threshold voltage occurs at 4.0 V. Above 4.0 V, the cell will read as holding data.
MLC Levels
|
|---|
Value
| State
|
|---|
00
| Completely Programmed
|
|---|
01
| Partially Programmed
|
|---|
10
| Partially Erased
|
|---|
11
| Completely Erased
|
|---|
If a Single-Level Cell holds one bit per cell, then a Multi-Level Cell obviously holds more than one. As shown in the table, we now are looking at two bits per cell. This comes out to four states. While that sounds great on paper, there is a cost to increasing storage density.
Flash memory only has so much voltage tolerance. You can't just double the voltage to multiply the scale. Instead, you need more sensitively between each state. This means more programming to manipulate a very precise amount of charge stored in the floating gate. MLC works in the same way SLC does, but with greater precision on charge placement and charge sensing.
Comparison of SLC and MLC (3x nm)
|
|---|
| SLC
| MLC
|
|---|
Bits/Cell
| 1
| 2
|
|---|
Density
| 16 Gb
| 32 Gb
|
|---|
Read Speed
| 100 ns
| 120 ns
|
|---|
Block Size
| 64 Kb
| 128 Kb
|
|---|
Endurance
| 100 000 cycles
| 3 000 cycles
|
|---|
ECC Capability
| 8 b/512 B
| 24 b/1 KB
|
|---|
tPROG
| 0.5 ms
| 1.2 ms
|
|---|
tERASE
| 1.5 - 2 ms
| 3 ms
|
|---|
Operating Temp
| Industrial
| Commercial
|
|---|
All of this means that you can use the same wafer size and get double the density with MLC. Of course, there is a penalty. First, accelerated degradation of the silicon channel is responsible for the lower endurance of MLC-based flash. This occurs because there is more activity, as it needs to pass different charges with greater frequency. Second, as you increase the precision, performance is affected. Remember that storing one bit is straightforward. The cell just has to be above or below 4 V.
SSDs (at least so far) only employ two-bit per cell MLC. As you keep increasing the density, you have to give up more and more performance and endurance, which is why three-bit per cell MLC is not what vendors call compute-quality yet. It's only used in devices like USB flash drives, removable flash cards, and portable media players.
